1. Field of the Invention
The present invention relates to a method of compacting layouts (mask patterns) of semiconductor integrated circuits. Particularly, the present invention relates to an improvement of the compaction procedure for compacting hierarchically arranged layouts.
2. Description of the Prior Art
A layout of a semiconductor integrated circuit generally consists of a plurality of lower level cell layouts and higher level cell layouts in a hierarchical structure. These lower level cell layouts and higher level cell layouts are coupled by wirings in interconnection areas designed together with the layout of the higher level cell layouts. In accordance with one approach to perform compaction of such layouts composed of a plurality of lower level cell layouts and higher level cell layouts in a hierarchical structure, all the lower level cell layouts are expanded to flatten the hierarchy into a single level layout followed by compaction of the single level layout. However, a usual compactor implemented with a standard EWS (engineering workstation) can deal only with semiconductor integrated circuits composed of up to about ten thousands transistors. More comprehensive semiconductor integrated circuits designed in higher integration levels can therefore not be compacted by this method.
Several approaches have been proposed to perform compaction of hierarchical layouts without resolving the hierarchy.
These approaches include the bottom-up method and the pitch-matching method. In accordance with the bottom-up method, the compaction is performed in sequence from the lowest level cell layouts to the highest level cell layouts. The interconnection between lower level cell layouts and higher level cell layouts is made by the river routing technique after compaction. In accordance with the river routing technique, single layered wirings are used to interconnect corresponding terminals of lower level cell layouts and higher level cell layouts arranged in the same order without intersection.
On the other hand, in accordance with the pitch-matching method, compaction is performed in order to maintain agreement of the positions of the terminals of lower level cell layouts with the positions of the corresponding terminals of higher level cell layouts at the boundaries between the lower level cell layouts and the higher level cell layouts. In this case, particular interconnection procedure is not needed after the compaction.
However, in accordance with the bottom-up method, when interconnection is made between lower level cell layouts and a higher level cell layout in accordance with the bottom-up method, since the terminals of the lower level cell layouts tend to depart from the corresponding terminals of the higher level cell layouts by compaction, the interconnection areas are therefore increased to make connection therebetween. Accordingly, the compaction ratio can not fully be reflected to the reduction of the chip size.
Contrary to this, in accordance with the pitch-matching method, the increase of the chip size due to the interconnection areas is avoided since the spatial correspondence between terminals of lower level cell layouts and higher level cell layouts is maintained just after compaction. However, this method is applicable only to the cases where there is some regularity between lower level cell layouts and higher level cell layouts.
The accompanying drawings, which are incorporated in and form a part of the invention and, together with the description, serve to explain the principles of the invention.